E2K. Technology and Implementation

by Professor Boris Babayan
Elbrus International

Abstract:

Basic technologies and implementation of the E2K microprocessor are described. The E2K microprocessor is a new design based on postRISC architecture developed by the team. The chip ensures the top logical speed. In a 0.18-micron process it has a clock frequency of 1.2 GHz and delivers 135 SPECint95 and 350 SPECfp95 with 256KB in-chip L2 Cache. In a 0.1-micron process it has a clock frequency of 2.2 GHz and delivers 410 SPECint95 and 960 SPECfp95. The E2K architecture is scalable and fits well future feature sizes due to various types of parallelism used on chip (ILP, SIMD, synchronous multithreading). Binary compilation technique developed by the team makes the microprocessor fully compatible with x86 platform. The E2K binary compilation is highly efficient, strictly compatible and transparent for the user. Implementation of the HW supported data types in the design ensures high security of programming, ease of program debugging and perfect memory protection. The HW supported secure programming can be extended over the entire Internet thus ensuring full, reliable and efficient solution of the virus protection problem.


Last modified: Thu Jun 8 10:17:18 MET DST 2000